Daedalus: A Framework for System-Level Design For Multi-Processor System-on-Chip
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This directory contains the Daedalus design flow for system-level design of multiprocessor system-on-chip (MPSoC). Given a C program written as a static affine nested loop program, it parallelizes the program and provides the ability to perform either SystemC simulation or platform synthesis targeting FPGA. The flow consists of the following stages:

1) **Parallelization** : In this stage, the C program is prarallelized using the [PNgen](http://repo.or.cz/w/isa.git) compiler to generate a parallel specification in the form of Polyhedral Process Network (PPN). 
    
2) **Design Space Exploration** : In this stage, the PPN produced in the previous step is analyzed to determine the hardware platform size needed to schedule it and the mapping of tasks to processors. The analysis is implemented using [Sesame](https://csa.science.uva.nl/)

3) **System Synthesis** : After stages 1 and 2, the flow produces three specifications:

* Applications Specifications: A description of the application in the polyhedral representation

* Platform Specifications: A description of the MPSoC hardware platform
    
* Mapping Specifications: The mapping of applications' tasks to processors derived by Sesame

These three specifications are passed as input to the [ESPAM](http://daedalus.liacs.nl/espam/) tool to synthesize the RTL and parallel code of the final system.


Using the flow
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We provide an easy demonstrator in the form of a script called `daedalus.sh`. This script accepts as an input a directory containing the C program which will be parallelized and mapped onto an MPSoC. To see the flow in action, simply execute `daedalus.sh` as follows:

	./scripts/daedalus.sh examples/sobel operation

where `operation` can take one of the following values:
`sequential` : Compiles and runs the sequential code of the C program
`parallel` : Parallelize the code using the PNgen compiler
`systemc-untimed` : Parallelize and simulate the resulting parallel code using Untimed SystemC backend
`systemc-timed` : Parallelize and simulate the resulting parallel code using Timed SystemC backend
`fpga` : Parallelize and synthesize the system using ESPAM to generate Xilinx Platform Studio project

The `examples` directory contains an example application which the Sobel image filter.


Further Information
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For further information about the flow, you can see the publications page. For further information on how to use it, please check the [Daedalus User Manual](http://daedalus.liacs.nl/).


Bugs/Issues
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In case of bugs/issues, please contact [Daedalus Support Email](csartem@liacs.nl)