daedalus-rt: a framework for automated design of hard-real-time embedded streaming systems
==========================================================================================

This directory contains the Daedalus^RT design flow for automated design of hard-real-time embedded streaming systems. Given a set of streaming applications written in C, it produces a synthesizable RTL description of a multiprocessor system-on-chip (MPSoC) platform together with the parallelized code of the applications. The flow consists of the following stages:

1) **Parallelization** : In this stage, the C code of each application is prarallelized using the [PNgen](http://repo.or.cz/w/isa.git) compiler. The parallelization phase itself consists of the following phases:

* Polyhedral Process Network (PPN) extraction
    
* Cyclo-Static Dataflow (CSDF) graph extraction
    
2) **Analysis** : In this stage, the CSDF graphs produced in the previous step are analyzed to determine the minimum number of processors needed to schedule them and the mapping of tasks to processors. The analysis is implemented using the [darts toolbox](http://daedalus.liacs.nl/darts/)

3) **System Synthesis** : After stages 1 and 2, the flow produces three specifications:

* Applications Specifications: A description of the applications functionality in the polyhedral representation

* Platform Specifications: A description of the minimum number of processors needed to schedule the applications using hard-real-time multiprocessor scheduling algorithms (e.g., Partitioned Earliest-Deadline-First and Fixed-Priority)
    
* Mapping Specifications: The mapping of applications' tasks to processors derived using bin packing heuristics (e.g., First-Fit, Worst-Fit)

These three specifications are passed as input to the [ESPAM](http://daedalus.liacs.nl/espam/) tool to synthesize the RTL and parallel code of the final system.


Using the flow
--------------
We provide an easy demonstrator in the form of a script called `daedalus-rt.sh`. This script accepts as an input a directory containing a set of C applications which will be mapped onto an MPSoC. To see the flow in action, simply execute `daedalus-rt.sh` as follows:

    > ./scripts/daedalus-rt.sh examples/synthetic
    
The `examples/synthetic` directory contains a set of example applications.


Deriving CSDF graphs from static affine nested-loop programs
------------------------------------------------------------
To derive a CSDF graph in the SDF3 XML format, you can use the script called `c2csdf.sh`. The script accepts the path to the file as input and produces the corresponding SDF3-compatible XML file.
For example, to generate the CSDF model of the `pipeline.c` application under the `examples/synthetic` directory, you can execute the following command:

    > ./scripts/c2csdf.sh examples/synthetic/pipeline.c

A directory called `pipeline_graphs` will be generated in `examples/synthetic` which contains the final SDF3-compatible XML specification with the name `pipeline.xml`


System Synthesis
----------------
The system synthesis stage is configured currently to generate a tiled distributed-memory homogeneous multiprocessor system-on-chip (MPSoC) which uses an AXI-4 crossbar switch as the on-chip interconnect. The generated platform uses Fixed-Priority Preemptive Scheduling (FPPS) using [FreeRTOS](http://www.freertos.org/) to schedule the tasks.


Further Information
-------------------
For further *theoretical* information about the flow, you can see the [DATE 2012 paper](http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6176632). For further information on how to use it, please check the [Daedalus User Manual](http://daedalus.liacs.nl/).


Bugs/Issues
-----------
In case of bugs/issues, please contact [Mohamed Bamakhrama](mohamed@liacs.nl) or [Teddy Zhai](tzhai@liacs.nl)


License
-------
Each tool of the flow is licensed according to its own license. The content of this directory is released under the BSD license shown in LICENSE.md